1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly a method which simplifies the processes by which a high voltage MOS (metal oxide semiconductor) transistor and a Bipolar transistor are manufactured in the same substrate.
2. Prior Art
BiMOS technology (bipolar and MOS transistors on a single semiconductor substrate) has become an increasingly attractive device technology because it can provide high performance (better than MOS alone) without high power consumption (much lower than bipolar alone). One of the recognized drawbacks in fabricating BiMOS devices is the increased processing required to produce both MOS and bipolar components on the same chip. This is because conventionally the processes remain separate, and thus the wafer must undergo two processing sequences, one for the bipolar transistor and one for the MOS transistor.
As shown by U.S. Pat. No. 4,868,135 a significant reduction in the number of steps used to produce both the bipolar transistor and a MOS transistor can be accomplished by using a process for fabricating the BiMOS device which includes certain common steps for the integration of the fabrication of the bipolar transistor and the MOS transistor. This process produces both the bipolar transistor and the MOS transistor simultaneously by incorporating similar structural features between the bipolar and the MOS transistors. A bipolar structure transistor is configured which is closer to and more compatible with that of the MOS transistors.
Normally, this type of process would be adequate for the production of both bipolar and MOS transistors on a single substrate, however, the MOS transistors fabricated by the above methodology are only good for a limited range of input voltages. These MOS transistors are only operable within normal, low voltage, ordinary applications. This process does not address the problem of specialized, high voltage applications where a MOS transistor of high breakdown voltage is needed.
When a high voltage MOS transistor is to be manufactured, the construction of the transistor and the method of manufacturing the transistor are determined upon consideration of the following problems:
(1) punch through phenomenon between the source and the drain in which a depletion layer extends to the source region if the length of the channel is small; PA1 (2) dielectric breakdown between the gate and the drain (sustaining breakdown voltage) and; PA1 (3) avalanche caused by the concentration of an electric field near the surface of the drain region which occurs when the drain region and the gate are overlaid with an interposed thin insulator film.
The present technology, as shown by U.S. Pat. No. 4,818,719, is that the above mentioned problems can be reduced, with a minimal impact on the device processing steps. This patent discloses a process where a first impurity region having a particular conduction type and serving as a channel stopper of the MOS transistor and a second impurity region having the same conduction type as the first impurity region and serving as an offset low doped layer of the high voltage MOS transistor are produced simultaneously. This type of transistor, with an offset low doped layer in the drain in addition to the usual drain layer, is often called a doubly diffused drain MOS transistor or a DMOS transistor. The offset low doped layer is often called a drift region. The drift region has a much lower impurity concentration then the adjacent drain area and connects the transistors gate region with the adjacent drain area. While this method provides a reasonably good high voltage transistor there is still considerable room for improvement in the sustaining breakdown voltage characteristics.
Improvements in the DMOS transistor alone resulting in better operating characteristics have been discussed in Process and Device Design of a 1000-v MOS IC by Tadanori Yamaguchi and Seiichi Morimoto in IEEE Trans. Electron Devices, vol ED-29, pp. 1171-1178, August 1982. This paper discusses a process sequence for making a double diffused drain (two separate increasing implant concentration regions) high voltage MOS transistor and contemplates extension of the process to a triple diffused drain (three separate increasing implant concentrations) high voltage MOS transistor to obtain high voltage transistors with preferred operating characteristics at the cost of increased processing steps.
In the above described conventional procedures, MOS transistors of ordinary low voltage logic operation may be fabricated in common with bipolar transistors. In order to fabricate a high voltage MOS transistor with a bipolar transistor it has been conventional for one skilled in the art to combine the separate processes steps as known for each technology into a combined processing sequence incorporating all the individual steps of both technologies. Since, the sustaining breakdown voltage of a MOS greatly depends on the concentration of the impurity in the drift region, the standard practice for fabricating a bipolar transistor and a high voltage MOS transistor in the same substrate has been to control the impurity concentrations for each transistor within their separate processes. This has resulted in overly complicated processing plans, which are undesirable as they contain excessive processing steps and are time consuming and costly. Some effort has been spent in the area of combining processing steps efficiently to produce high voltage MOS transistors (U.S. Pat. No. 4,818,719) but this effort has not been directed at producing high voltage MOS transistors in an efficient manner with bipolar transistors because the resulting process sequences have been unduly burdensome.